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DFLIPFLOP

D flip-flop

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Description

That block outputs on Q its input state (D) when the enable input (en) is set and on the rising edge of the clock input (clk). The !Q output is the logical negation of Q. This flip-flop is also known as a delay flip-flop because the state of the input is modified only at the next rising edge of the clock.

The D flip-flop is used as a basic cell of shift-registers.

The truth table of this block is the following:

clk en D Qn !Qn
0 X Qn-1 !Qn-1
1 0 0 1
1 1 1 0
Non-Rising X X Qn-1 !Qn-1

where X stands for "indifferent" and Qn-1 is the previous output state of Qn .

Data types

The block supports the following types :

Default properties

Interfacing function

See also


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